//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
//Date        : Mon Sep 26 10:15:48 2016
//Host        : localhost.localdomain running 64-bit CentOS release 6.3 (Final)
//Command     : generate_target design_1_wrapper.bd
//Design      : design_1_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module dpsm_top (
    input  wire        CLK_P, 
    output wire        RS232_Uart_1_sout,
    input  wire        RS232_Uart_1_sin,
    inout  wire        MCB_DDR3_rzq,
    output wire        MCB_DDR3_dram_we_n,
    inout  wire        MCB_DDR3_dram_udqs_n,
    inout  wire        MCB_DDR3_dram_udqs,
    output wire        MCB_DDR3_dram_udm,
    output wire        MCB_DDR3_dram_ras_n,
    output wire        MCB_DDR3_dram_odt,
    output wire        MCB_DDR3_dram_ldm,
    inout  wire        MCB_DDR3_dram_dqs_n,
    inout  wire        MCB_DDR3_dram_dqs,
    inout  wire[15:0]  MCB_DDR3_dram_dq,
    output wire        MCB_DDR3_dram_ddr3_rst,
    output wire        MCB_DDR3_dram_clk_n,
    output wire        MCB_DDR3_dram_clk,
    output wire        MCB_DDR3_dram_cke,
    output wire        MCB_DDR3_dram_cas_n,
    output wire[2:0]   MCB_DDR3_dram_ba,
    output wire[12:0]  MCB_DDR3_dram_addr,

    output wire        camerax_xclk,
    output wire        camerax_pwrdown,
    output wire        camerax_resetn,

    input  wire        camera0_pclk, 
    input  wire [7:0]  camera0_yuv , 
    input  wire        camera0_h_sync, 
    input  wire        camera0_v_sync, 
    output wire        camera0_sclk,
    inout  wire        camera0_sda ,

    input  wire        camera1_pclk, 
    input  wire [7:0]  camera1_yuv , 
    input  wire        camera1_h_sync, 
    input  wire        camera1_v_sync, 
    output wire        camera1_sclk,
    inout  wire        camera1_sda,

    output wire        txout0_p,
    output wire        txout0_n,
    output wire        txout1_p,
    output wire        txout1_n,
    output wire        txout2_p,
    output wire        txout2_n,
    output wire        txout3_p,
    output wire        txout3_n,
    output wire        txclk_p,
    output wire        txclk_n,
    
    output wire        QSPI_sck,
    output wire        QSPI_ss,
    inout  wire        QSPI_io0,
    inout  wire        QSPI_io1,

    input  wire[7:0]   tp_key,

    output wire        motor_en,
    output wire        motor_rstn,
 
    output wire        motor_stp_l,
    output wire        motor_stp_r,
    output wire        motor_stp_x,
    output wire        motor_stp_y,

    output wire        motor_dir_l,
    output wire        motor_dir_r,
    output wire        motor_dir_x,
    output wire        motor_dir_y,
 
    output wire [1:0]  motor_mod_l,
    output wire [1:0]  motor_mod_r,
    output wire [1:0]  motor_mod_x,
    output wire [1:0]  motor_mod_y,    

    output wire        adc_scl,
    inout  wire        adc_sda,

    output wire        dac_sclk,
    output wire        dac_sdata,
    output wire        dac_load,
    output wire        gaoya,

    output wire        rtc_scl,
    inout  wire        rtc_sda,

    output wire        eeprom_scl,
    inout  wire        eeprom_sda 
);

wire[15:0]  key_in;

assign key_in = {8'hff,~tp_key};

wire        FCLK_24Mhz  ;
wire        FCLK_140Mhz ;
wire        FCLK_100Mhz ;
wire        FRESETn;
wire        reset_n;
wire        clk_iic_cp;
wire        clk_cp;
wire        key_intr;
wire        QSPI_spisel = 1'b1;

wire[31:0]  VGA_AXI_ARADDR;
wire[7:0]   VGA_AXI_ARLEN;
wire[2:0]   VGA_AXI_ARSIZE;
wire[1:0]   VGA_AXI_ARBURST;
wire[3:0]   VGA_AXI_ARCACHE;
wire[2:0]   VGA_AXI_ARPROT;
wire        VGA_AXI_ARVALID;
wire        VGA_AXI_ARREADY;
wire [31:0] VGA_AXI_RDATA;
wire [1:0]  VGA_AXI_RRESP;
wire        VGA_AXI_RLAST;
wire        VGA_AXI_RVALID;
wire        VGA_AXI_RREADY;

wire [31:0] REGS_AXI_AWADDR;
wire        REGS_AXI_AWVALID;
wire        REGS_AXI_AWREADY;
wire [31:0] REGS_AXI_WDATA;
wire [3:0]  REGS_AXI_WSTRB;
wire        REGS_AXI_WVALID;
wire        REGS_AXI_WREADY;
wire[1:0]   REGS_AXI_BRESP;
wire        REGS_AXI_BVALID;
wire        REGS_AXI_BREADY;
wire [31:0] REGS_AXI_ARADDR;
wire        REGS_AXI_ARVALID;
wire        REGS_AXI_ARREADY;
wire[31:0]  REGS_AXI_RDATA;
wire[1:0]   REGS_AXI_RRESP;
wire        REGS_AXI_RVALID;
wire        REGS_AXI_RREADY;

wire[31:0]  CAMERA_AXI_AWADDR;
wire[7:0]   CAMERA_AXI_AWLEN;
wire[2:0]   CAMERA_AXI_AWSIZE;
wire[1:0]   CAMERA_AXI_AWBURST;
wire[3:0]   CAMERA_AXI_AWCACHE;
wire[2:0]   CAMERA_AXI_AWPROT;
wire        CAMERA_AXI_AWVALID;
wire        CAMERA_AXI_AWREADY;
wire[31:0]  CAMERA_AXI_WDATA;
wire[3:0]   CAMERA_AXI_WSTRB;
wire        CAMERA_AXI_WLAST;
wire        CAMERA_AXI_WVALID;
wire        CAMERA_AXI_WREADY;
wire [1:0]  CAMERA_AXI_BRESP;
wire        CAMERA_AXI_BVALID;
wire        CAMERA_AXI_BREADY;

BUFG g_inst0
(
    .I ( clk_cp     ),
    .O ( clk_iic_cp )
);

S_RESET s_0( 
    .clk      ( CLK_P      ) ,  
    .sclk     ( clk_iic_cp ) ,
    .reset_i  ( 1'b1       ) , 

    .reset_n  ( reset_n ) 
); 

/*
//--------------------------------------------------------
wire   a100m_resetn = VGA_AXI_ARESETN;
wire   clkfb;

wire   pl_24mhz_p         ;
wire   pl_24mhz_n         ;
wire   pl_175mhz          ;
wire   pl_24mhz_lock      ;

//--------------------------------------------------------
clk_wiz_pixl  clk_wiz_pixl_inst0(
    .clk_in_25m    ( clk_25mhz   ),
    .clk_out_24m_p ( pl_24mhz_p  ),
    .clk_out_24m_n ( pl_24mhz_n  ),
    .clk_out_175m  ( pl_175mhz   ),
    
    .CLKFB_IN      ( clkfb       ),
    .CLKFB_OUT     ( clkfb       ),
    .reset         ( ~a100m_resetn  ),
    .locked        ( pl_24mhz_lock  )
);
*/

ODDR2 #(
    .DDR_ALIGNMENT( "NONE" ), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT         ( 1'b0   ), // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE       ( "SYNC" )  // Specifies "SYNC" or "ASYNC" set/reset
) 
XCLK_inst0
(
    .Q   ( camerax_xclk  ),   // 1-bit DDR output data
    .C0  ( FCLK_24Mhz    ),   // 1-bit clock input
    .C1  ( ~FCLK_24Mhz   ),   // 1-bit clock input
    .CE  ( 1'b1          ), // 1-bit clock enable input
    .D0  ( 1'b1          ), // 1-bit data input (associated with C0)
    .D1  ( 1'b0          ), // 1-bit data input (associated with C1)
    .R   ( 1'b0          ),   // 1-bit reset input
    .S   ( 1'b0          )    // 1-bit set input
);

system_top cpu_top_inst0
(    
    .CLK_P                  ( CLK_P                  ) ,
    .RESET                  ( reset_n                ) ,
    .UART_TX                ( RS232_Uart_1_sout      ) ,
    .UART_RX                ( RS232_Uart_1_sin       ) ,

    .FCLK_24Mhz             ( FCLK_24Mhz             ) ,
    .FCLK_100Mhz            ( FCLK_100Mhz            ) ,
    .FCLK_140Mhz            ( FCLK_140Mhz            ) ,
    .FRESETn                ( FRESETn                ) ,
    .Tp_Intr                ( key_intr               ) ,

    .QSPI_SPISEL            ( QSPI_spisel            ) ,
    .QSPI_SCK               ( QSPI_sck               ) ,
    .QSPI_SS                ( QSPI_ss                ) ,
    .QSPI_IO0               ( QSPI_io0               ) ,
    .QSPI_IO1               ( QSPI_io1               ) ,

    .MCB_DDR3_rzq           ( MCB_DDR3_rzq           ) ,
    .MCB_DDR3_dram_we_n     ( MCB_DDR3_dram_we_n     ) ,
    .MCB_DDR3_dram_udqs_n   ( MCB_DDR3_dram_udqs_n   ) ,
    .MCB_DDR3_dram_udqs     ( MCB_DDR3_dram_udqs     ) ,
    .MCB_DDR3_dram_udm      ( MCB_DDR3_dram_udm      ) ,
    .MCB_DDR3_dram_ras_n    ( MCB_DDR3_dram_ras_n    ) ,
    .MCB_DDR3_dram_odt      ( MCB_DDR3_dram_odt      ) ,
    .MCB_DDR3_dram_ldm      ( MCB_DDR3_dram_ldm      ) ,
    .MCB_DDR3_dram_dqs_n    ( MCB_DDR3_dram_dqs_n    ) ,
    .MCB_DDR3_dram_dqs      ( MCB_DDR3_dram_dqs      ) ,
    .MCB_DDR3_dram_dq       ( MCB_DDR3_dram_dq       ) ,
    .MCB_DDR3_dram_ddr3_rst ( MCB_DDR3_dram_ddr3_rst ) ,
    .MCB_DDR3_dram_clk_n    ( MCB_DDR3_dram_clk_n    ) ,
    .MCB_DDR3_dram_clk      ( MCB_DDR3_dram_clk      ) ,
    .MCB_DDR3_dram_cke      ( MCB_DDR3_dram_cke      ) ,
    .MCB_DDR3_dram_cas_n    ( MCB_DDR3_dram_cas_n    ) ,
    .MCB_DDR3_dram_ba       ( MCB_DDR3_dram_ba       ) ,
    .MCB_DDR3_dram_addr     ( MCB_DDR3_dram_addr     ) ,

    .VGA_AXI_ARADDR         ( VGA_AXI_ARADDR         ) ,
    .VGA_AXI_ARLEN          ( VGA_AXI_ARLEN          ) ,
    .VGA_AXI_ARSIZE         ( VGA_AXI_ARSIZE         ) ,
    .VGA_AXI_ARBURST        ( VGA_AXI_ARBURST        ) ,
    .VGA_AXI_ARCACHE        ( VGA_AXI_ARCACHE        ) ,
    .VGA_AXI_ARPROT         ( VGA_AXI_ARPROT         ) ,
    .VGA_AXI_ARVALID        ( VGA_AXI_ARVALID        ) ,
    .VGA_AXI_ARREADY        ( VGA_AXI_ARREADY        ) ,
    .VGA_AXI_RDATA          ( VGA_AXI_RDATA          ) ,
    .VGA_AXI_RRESP          ( VGA_AXI_RRESP          ) ,
    .VGA_AXI_RLAST          ( VGA_AXI_RLAST          ) ,
    .VGA_AXI_RVALID         ( VGA_AXI_RVALID         ) ,
    .VGA_AXI_RREADY         ( VGA_AXI_RREADY         ) ,
    
    .REGS_AXI_AWADDR        ( REGS_AXI_AWADDR        ) ,
    .REGS_AXI_AWVALID       ( REGS_AXI_AWVALID       ) ,
    .REGS_AXI_AWREADY       ( REGS_AXI_AWREADY       ) ,
    .REGS_AXI_WDATA         ( REGS_AXI_WDATA         ) ,
    .REGS_AXI_WSTRB         ( REGS_AXI_WSTRB         ) ,
    .REGS_AXI_WVALID        ( REGS_AXI_WVALID        ) ,
    .REGS_AXI_WREADY        ( REGS_AXI_WREADY        ) ,
    .REGS_AXI_BRESP         ( REGS_AXI_BRESP         ) ,
    .REGS_AXI_BVALID        ( REGS_AXI_BVALID        ) ,
    .REGS_AXI_BREADY        ( REGS_AXI_BREADY        ) ,
    .REGS_AXI_ARADDR        ( REGS_AXI_ARADDR        ) ,
    .REGS_AXI_ARVALID       ( REGS_AXI_ARVALID       ) ,
    .REGS_AXI_ARREADY       ( REGS_AXI_ARREADY       ) ,
    .REGS_AXI_RDATA         ( REGS_AXI_RDATA         ) ,
    .REGS_AXI_RRESP         ( REGS_AXI_RRESP         ) ,
    .REGS_AXI_RVALID        ( REGS_AXI_RVALID        ) ,
    .REGS_AXI_RREADY        ( REGS_AXI_RREADY        ) ,

    .CAMERA_AXI_AWADDR      ( CAMERA_AXI_AWADDR      ) ,
    .CAMERA_AXI_AWLEN       ( CAMERA_AXI_AWLEN       ) ,
    .CAMERA_AXI_AWSIZE      ( CAMERA_AXI_AWSIZE      ) ,
    .CAMERA_AXI_AWBURST     ( CAMERA_AXI_AWBURST     ) ,
    .CAMERA_AXI_AWCACHE     ( CAMERA_AXI_AWCACHE     ) ,
    .CAMERA_AXI_AWPROT      ( CAMERA_AXI_AWPROT      ) ,
    .CAMERA_AXI_AWVALID     ( CAMERA_AXI_AWVALID     ) ,
    .CAMERA_AXI_AWREADY     ( CAMERA_AXI_AWREADY     ) ,
    .CAMERA_AXI_WDATA       ( CAMERA_AXI_WDATA       ) ,
    .CAMERA_AXI_WSTRB       ( CAMERA_AXI_WSTRB       ) ,
    .CAMERA_AXI_WLAST       ( CAMERA_AXI_WLAST       ) ,
    .CAMERA_AXI_WVALID      ( CAMERA_AXI_WVALID      ) ,
    .CAMERA_AXI_WREADY      ( CAMERA_AXI_WREADY      ) ,
    .CAMERA_AXI_BRESP       ( CAMERA_AXI_BRESP       ) ,
    .CAMERA_AXI_BVALID      ( CAMERA_AXI_BVALID      ) ,
    .CAMERA_AXI_BREADY      ( CAMERA_AXI_BREADY      ) 
);
 
FUSION_TOP  FUSION_TOP_inst0 
(  
    .REGS_AXI_ACLK          ( FCLK_100Mhz            ) , 
    .REGS_AXI_ARESETN       ( FRESETn                ) ,
    .REGS_AXI_ARADDR        ( REGS_AXI_ARADDR        ) , 
    .REGS_AXI_ARREADY       ( REGS_AXI_ARREADY       ) , 
    .REGS_AXI_ARVALID       ( REGS_AXI_ARVALID       ) , 
    .REGS_AXI_AWADDR        ( REGS_AXI_AWADDR        ) , 
    .REGS_AXI_AWREADY       ( REGS_AXI_AWREADY       ) , 
    .REGS_AXI_AWVALID       ( REGS_AXI_AWVALID       ) , 
    .REGS_AXI_BREADY        ( REGS_AXI_BREADY        ) , 
    .REGS_AXI_BRESP         ( REGS_AXI_BRESP         ) , 
    .REGS_AXI_BVALID        ( REGS_AXI_BVALID        ) , 
    .REGS_AXI_RDATA         ( REGS_AXI_RDATA         ) , 
    .REGS_AXI_RREADY        ( REGS_AXI_RREADY        ) , 
    .REGS_AXI_RRESP         ( REGS_AXI_RRESP         ) , 
    .REGS_AXI_RVALID        ( REGS_AXI_RVALID        ) , 
    .REGS_AXI_WDATA         ( REGS_AXI_WDATA         ) , 
    .REGS_AXI_WREADY        ( REGS_AXI_WREADY        ) , 
    .REGS_AXI_WSTRB         ( REGS_AXI_WSTRB         ) , 
    .REGS_AXI_WVALID        ( REGS_AXI_WVALID        ) , 

    .VGA_AXI_ACLK           ( FCLK_100Mhz            ) ,  
    .VGA_AXI_ARESETN        ( FRESETn                ) , 
    .VGA_AXI_ARADDR         ( VGA_AXI_ARADDR         ) ,
    .VGA_AXI_ARLEN          ( VGA_AXI_ARLEN          ) ,
    .VGA_AXI_ARSIZE         ( VGA_AXI_ARSIZE         ) ,
    .VGA_AXI_ARBURST        ( VGA_AXI_ARBURST        ) ,
    .VGA_AXI_ARCACHE        ( VGA_AXI_ARCACHE        ) ,
    .VGA_AXI_ARPROT         ( VGA_AXI_ARPROT         ) ,
    .VGA_AXI_ARVALID        ( VGA_AXI_ARVALID        ) ,
    .VGA_AXI_ARREADY        ( VGA_AXI_ARREADY        ) ,
    .VGA_AXI_RDATA          ( VGA_AXI_RDATA          ) ,
    .VGA_AXI_RRESP          ( VGA_AXI_RRESP          ) ,
    .VGA_AXI_RLAST          ( VGA_AXI_RLAST          ) ,
    .VGA_AXI_RVALID         ( VGA_AXI_RVALID         ) ,
    .VGA_AXI_RREADY         ( VGA_AXI_RREADY         ) ,

    .CAMERA_AXI_ACLK        ( FCLK_100Mhz            ) ,  
    .CAMERA_AXI_ARESETN     ( FRESETn                ) , 
    .CAMERA_AXI_AWADDR      ( CAMERA_AXI_AWADDR      ) ,
    .CAMERA_AXI_AWLEN       ( CAMERA_AXI_AWLEN       ) ,
    .CAMERA_AXI_AWSIZE      ( CAMERA_AXI_AWSIZE      ) ,
    .CAMERA_AXI_AWBURST     ( CAMERA_AXI_AWBURST     ) ,
    .CAMERA_AXI_AWCACHE     ( CAMERA_AXI_AWCACHE     ) ,
    .CAMERA_AXI_AWPROT      ( CAMERA_AXI_AWPROT      ) ,
    .CAMERA_AXI_AWVALID     ( CAMERA_AXI_AWVALID     ) ,
    .CAMERA_AXI_AWREADY     ( CAMERA_AXI_AWREADY     ) ,
    .CAMERA_AXI_WDATA       ( CAMERA_AXI_WDATA       ) ,
    .CAMERA_AXI_WSTRB       ( CAMERA_AXI_WSTRB       ) ,
    .CAMERA_AXI_WLAST       ( CAMERA_AXI_WLAST       ) ,
    .CAMERA_AXI_WVALID      ( CAMERA_AXI_WVALID      ) ,
    .CAMERA_AXI_WREADY      ( CAMERA_AXI_WREADY      ) ,
    .CAMERA_AXI_BRESP       ( CAMERA_AXI_BRESP       ) ,
    .CAMERA_AXI_BVALID      ( CAMERA_AXI_BVALID      ) ,
    .CAMERA_AXI_BREADY      ( CAMERA_AXI_BREADY      ) ,

    .clk_7x_vga             ( FCLK_140Mhz            ) ,
    .key_in                 ( key_in                 ) ,
    .key_intr               ( key_intr               ) ,

    .rtc_scl                ( rtc_scl                ) ,
    .rtc_sda                ( rtc_sda                ) ,

    .eeprom_scl             ( eeprom_scl             ) ,
    .eeprom_sda             ( eeprom_sda             ) ,

    .adc_scl                ( adc_scl                ) ,
    .adc_sda                ( adc_sda                ) ,

    .dac_sclk               ( dac_sclk               ) ,
    .dac_sdata              ( dac_sdata              ) ,
    .dac_load               ( dac_load               ) ,
    .gaoya                  ( gaoya                  ) ,

    .camerax_pwrdown        ( camerax_pwrdown        ) ,
    .camerax_resetn         ( camerax_resetn         ) ,

    .camera0_pclk           ( camera0_pclk           ) ,
    .camera0_yuv            ( camera0_yuv            ) ,
    .camera0_h_sync         ( camera0_h_sync         ) ,
    .camera0_v_sync         ( camera0_v_sync         ) ,
    .camera0_sclk           ( camera0_sclk           ) ,
    .camera0_sda            ( camera0_sda            ) ,

    .camera1_pclk           ( camera1_pclk           ) ,
    .camera1_yuv            ( camera1_yuv            ) ,
    .camera1_h_sync         ( camera1_h_sync         ) ,
    .camera1_v_sync         ( camera1_v_sync         ) ,
    .camera1_sclk           ( camera1_sclk           ) ,
    .camera1_sda            ( camera1_sda            ) ,

    .motor_en               ( motor_en               ) ,
    .motor_rstn             ( motor_rstn             ) ,
  
    .motor_stp_l            ( motor_stp_l            ) ,
    .motor_stp_r            ( motor_stp_r            ) ,
    .motor_stp_x            ( motor_stp_x            ) ,
    .motor_stp_y            ( motor_stp_y            ) ,
   
    .motor_dir_l            ( motor_dir_l            ) ,
    .motor_dir_r            ( motor_dir_r            ) ,
    .motor_dir_x            ( motor_dir_x            ) ,
    .motor_dir_y            ( motor_dir_y            ) ,
    
    .motor_mod_l            ( motor_mod_l            ) ,
    .motor_mod_r            ( motor_mod_r            ) ,
    .motor_mod_x            ( motor_mod_x            ) ,
    .motor_mod_y            ( motor_mod_y            ) ,   

    .txout0_p               ( txout0_p               ) ,
    .txout0_n               ( txout0_n               ) ,
    .txout1_p               ( txout1_p               ) ,
    .txout1_n               ( txout1_n               ) ,
    .txout2_p               ( txout2_p               ) ,
    .txout2_n               ( txout2_n               ) ,
    .txout3_p               ( txout3_p               ) ,
    .txout3_n               ( txout3_n               ) ,
    .txclk_p                ( txclk_p                ) ,
    .txclk_n                ( txclk_n                ) 
);



endmodule

